Integrated circuits are formed from semiconductor substrates, usually silicon (Si), within and upon whose surfaces are formed active semiconductor regions containing electrical circuit elements that are internally and externally connected to the substrate through multiple patterned conductor layers that are separated by dielectric layers. These active semiconductor regions must be otherwise electrically isolated from adjacent active semiconductor regions by the formation of intervening trenches which are subsequently filled with dielectric material to ensure such electrical isolation and avoid undesired interference between adjacent active semiconductor regions. The continued miniaturization of integrated circuit devices has resulted in smaller trenches formed by, for example, shallow trench isolation (STI) methods to form trench isolation regions essentially co-planar with adjacent active semiconductor regions of the semiconductor substrates.
As noted in U.S. Pat. No. 5,741,740 to Jang et al., it has been found that filling these isolation trenches with gap filling silicon oxide layers through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition methods produce superior results as the silicon oxide layers typically possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions usually present in advanced integrated circuit fabrication.
However, for these increasingly miniaturized integrated circuits with corresponding miniaturized shallow isolation trenches having a width of less than about 0.26 microns, or side walls that are greater than about 80.degree. vertical, an undesired void, or keyhole, is formed within the gap filling silicon oxide layer within the trench. It is easy to form an overhead at the top corners of shallow trenches using traditional CVD-ox (chemical vapor deposition of silicon oxide) to gap filling and thus voids are formed. Void defects may trap contamination or make the final oxide surface of the STI (shallow trench isolation region) lower than the active surface. Also, junction leakage would increase.
For example, U.S. Pat. No. 4,506,435 to Pliskin et al. describes first lining the trench with a silicon oxide lining then filling the trench with, for example, a borosilicate glass. The borosilicate glass layer is heated, causing it to soften and flow to approach planarity. Then the borosilicate glass layer and SiN mask layer are etched to make the borosilicate glass filled trench substantially planar with the SiO masking layer.
U.S. Pat. No. 5,099,304 to Takemura describes a STI fill process that: lines the trench with a silicon oxide lining; forming a silicon nitride (SiN) film over the silicon oxide lining; building a polycrystal silicon film over the SiN film; etching back the polycrystal silicon film below the surface of the semiconductor substrate; then filling the trench with a boron phosphorus doped CVD silicon glass (boron phosphosilicate). The boron phosphorus doped silicon oxide is heated to allow the boron phosphorus doped silicon glass (BPSG) to reflow and make the surface thereof flat. A silicon oxide film, e.g. a boron phosphosilicate glass film is built up by a low pressure CVD method over the semiconductor substrate to make an even flatter surface.
U.S. Pat. No. 4,740,480 to Ooka describes a BPSG isolation fill layer that is fused to flow and reflow to make a smoothly contoured or round surface.
U.S. Pat. No. 5,225,358 to Pasch describes a method where a BPSG layer forms both the STI oxide, filling the trench(es), and the inter level dielectric (ILD) layer after the transistor fabrication process. The BPSG layer is planarized by chemical mechanical polishing (CMP).
U.S. Pat. No. 5,811,345 to Yu et al. describes a SA-CVD-OX trench fill process with an ozone-TEOS layer over a phosphorus doped silicon oxide layer. The ozone-TEOS layer is lowered by a wet dip in HF solution then planarized by plasma etching down to the phosphorus doped silicon oxide layer without CMP being used.